Many electronics applications and systems require the use of one or more signals having particular frequencies and/or phases. For example, radio transmitters and receivers frequently employ local oscillator signals for upconversion and downconversion. Accordingly, methods and devices have been developed for generating such signals, including phase locked loop (PLL) based solutions.
Another device that may be used to generate signals is the direct digital synthesizer (DDS). Typically, a DDS receives an input clock signal and a control word. Based on the control word and possibly also on subsequent timing (Read, Write, Update control, etc.), the DDS outputs a waveform (e.g., a sine wave) having a known frequency and/or phase with respect to the input clock signal. For example, a DDS generally includes a phase accumulator to indicate a phase state of the current output sample and a lookup table to indicate an amplitude corresponding to that phase state. The control word may be loaded into a register of the DDS such as, for example, an accumulator. The DDS then determines the desired frequency and/or phase of the output signal based on the lookup table information associated with the received input control word. DDS devices available from integrated circuit suppliers include the AD98XX series products available from Analog Devices, Inc. of Norwood, Mass. Other DDS suppliers include Harris Corporation of Melbourne, Fla.; Intersil Corporation of Melbourne, Fla.; and Intel Corporation of Santa Clara, Calif.
A standard DDS may include a phase accumulator, a phase-to-amplitude converter, and a Digital to Analog Converter (DAC). The DDS core described above without the DAC may also be referred to as a Numerically Controlled Oscillator (NCO). The phase accumulator, phase-to-amplitude converter, and DAC are the standard building blocks for the DDS, although the implementation of each varies from design to design.
One such variance is the implementation of the phase-to-amplitude converter. This converter, which generally uses a look-up table stored in memory, receives the phase at a given sample and outputs a corresponding amplitude. However, in such implementations, only the most significant portion of the phase value may be used due to memory size limitations of current designs. Therefore the table truncates the X least significant bits (where X may change from design-to-design and part-to-part), using only the Y most significant bits. Additionally, the implementation of the table may change. For example, the amplitude may be repeated in 90 degree increments and only the sign of the amplitude may change according to the quadrant. Therefore many look-up tables use only 90 degrees in the look-up table along with a sign bit(s) to specify what quadrant the phase is in.
A DDS may be configured as a frequency divider. In such cases, the control word may specify a desired frequency and/or phase of the output signal (where the frequency is processed through the DDS core and any phase offset is summed in) as the ratio of the desired output signal to the input clock signal (where the output frequency is based on the accumulator value and the clock rate).
Because the DDS output is produced using a digital process, DDS based solutions may provide a significant reduction in phase noise as compared to analog based solutions. For example, analog solutions may use an error correction loop to determine the phase/frequency of the output. In such case, the transfer function that determines the extent (e.g., bandwidth) of correction is inversely proportional to the time required to correct, thereby sacrificing speed for phase noise or vice versa. Furthermore, DDS based solutions can provide fine tuning resolution of the output frequency (e.g., micro-hertz tuning resolution) as well as sub-degree phase tuning. In addition, DDS based solutions may provide such advantages as an extremely fast speed in tuning to the output frequency or phase, phase-continuous frequency switching with no over/undershoot, and little or no settling time as may occur for analog based (e.g. loop) solutions. DDS based solutions may also reduce or eliminate the need for manual system tuning and tweaking due to component aging and temperature drift, for example, that are often issues for analog based solutions.
However, DDS based solutions may require relatively high input clock speeds and may produce spurious frequency responses in which unwanted components are present in the output frequency spectrum.
One source of spurious output components (or “spurs”) is phase truncation error. Phase truncation error may occur, for example, when the number of entries in the DDS output lookup table is less than the maximum number of possible amplitudes capable of being specified by the digital control word based on, for example, the length of the accumulator register in the DDS which receives the control word for decoding. For example, a DDS with a 32-bit phase accumulator is capable of distinctly specifying 232 distinct phases. To provide corresponding amplitude entries for each of these 232 possibilities would require a phase lookup table containing 4,294,967,296 entries, which may not be feasible to provide in a design. Therefore, the lookup table may include less than the maximum number of possible amplitudes, and the DDS may resolve or correlate the phase accumulator value resulting from an input control word to that phase which is closest to the exact value specified by the state of the phase accumulator.
Furthermore, the amplitude of the truncation error spurs may vary periodically over time based on the overflow characteristic of the phase accumulator (also known as the Grand Repetition Rate). The change in truncation error amplitude with respect to time may define a periodic waveform having a frequency spectrum of sufficiently high range that higher order harmonics of the truncation error waveform produce aliasing into the Nyquist bandwidth. Additional information regarding DDS phase truncation and other errors and spurious responses is available from industry sources including, for example, “A Technical Tutorial on Digital Signal Synthesis” (published by Analog Devices, Inc., 1999.
Spurious responses may appear at frequencies relatively close to the output frequency of a DDS. This aspect can be particularly troublesome to system designers. In narrowband applications, the DDS input clock can be set to a single frequency or a very narrow tuning band, for example, to avoid these “close in” responses. However, thus restricting the range of the input clock also limits the output signal tuning range of the DDS.
Errors in the digital-to-analog conversion (DAC) process are typically a significant source of spurious responses. Such errors may include quantization error as well as DAC nonlinearities. DAC-introduced error, which may be related to the clock and the output frequencies, is typically highly predictable.